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iability, and production throughput. For example, for the a-Si:H TFT, the inverted staggered structure gives better mobility, threshold voltage and current on/off ration. For the poly-Si TFT, the conventional coplanar structure shows a high leakage current and serious kink and hot carrier effects. Although grain boundary hydrogenation can be used to solve the problem, altered transistor structures, such as the multiple gate, offset gate, field-induced drain, double gate, buried channel, or vertical channel, are also effective.⁶⁶⁾ Many of these new structures also showed improved transistor characteristics, such as a large on current, due to the increased channel width/length ratio. Recently, the aggressive shrinking of the channel length of the MOSFET imposes a great challenge to the lithography area. While it takes a long time to develop the manufacturable sub 50 nm lithography equipment and process, new transistor structures, such as the FinFET and dual gate, have also been proposed.^67,68) Some of the MESFET structures are similar to the above poly-Si structures.

Previously, it was discussed that the throughput of the TFT production could be increased by reducing process steps, such as using new transistor structures. For example, the a-Si:H TFT can be fabricated with only two masks.⁴⁰⁾ In another case, the complete a-Si:H TFT array with the storage capacitor could be fabricated with 4 – 5 masks.39) Even the complete CMOSFETs can be fabricated with five masking steps.⁴¹⁾ Therefore, TFT and ULSIC experiences in using new transistor structures to improve device performance or production throughput can benefit each other.

3. Future Applications and Collaborations

Since MOSFETs approaching the nano size, the ULSIC chip will eventually contain giga number of transistors operated in the tera-hertz frequency. This is achievable due to the near-perfect single crystal wafer substrate as well as years of advancements in fabrication processes and understanding of device physics. Although the single electron device has been demonstrated,^69,70) the physical limitation of the MOSFET size, e.g., the channel length, has not been determined. Additionally, there are constant efforts in creating optical devices based on the silicon technology. The recent demonstration of light emission from the nanocrystalline silicon embedded SiO2 ^71,72) expanded ULSIC to optical memories and possible interconnects.

The major advantage of the a-Si:H TFT is its low process temperature, which removes many limits on the substrate material and size. Its structures and composing materials are easy to alter to satisfy application needs. The a-Si:H TFT can be connected to many organic or inorganic materials or devices. The product’s sensing function may be further enhanced with the low- or high-speed TFT circuit, which is an unexplored area with much potential. Separately, the lowtemperature a-Si:H TFT nonvolatile memories have been demonstrated.²⁴⁾ Therefore, in spite of its low mobility, the a-Si:H TFT can be used to drive or to operate as a chemical, electrical, biological, and optical sensor.^11,73–81)

Although the field effect mobility of the individual poly-Si TFT can be as high as or even higher than that of a MOSFET,⁸²⁾ the current poly-TFT circuit speed is usually slower than that of the ULSIC, e.g., GHz vs >GHz.¹⁴⁾ However, the former is fabricated on the low-cost glass substrate at a medium temperature, e.g., 550 ^oC, which has advantages of the low production cost and the large product size. In principle, the poly-Si TFT circuit can be fabricated on a flexible substrate using a low-temperature process. The poly-Si TFT is especially useful in driving devices that require a large current, such as the organic LED^.83) Poly-Si TFT characteristics are often controlled by the bulk grain quality and grain boundary defect states. Since it is difficult to control the number and location of grain boundaries in the channel region in a large-area array, the reliability of the nano-size poly-Si TFT is a major concern. There are several methods being proposed to selectively forming the channel region within the single large grain,^84–86) which are potential solutions for the problem. However, in addition to further improve the grain quality, the transistor structure, channel location, and circuit layout need to be optimized⁸⁷⁾ before the poly-Si TFT circuit can compete with the ULSIC in speed.

Although TFT and ULSIC applications are expected to expand in different areas, there are overlapped areas, as shown in Fig. 7. Different technologies may be integrated into the same product. An example is the three-dimensional (3D) ‘‘smart chip’’ design, as shown in Fig. 8. The front end process of the ULSIC can be fabricated with the conventional process. Then, the high-speed poly-Si TFTs can be constructed above it using the high-temperature or laser crystallization process. Subsequently, the slower poly-Si TFTs can be fabricated away from the wafer with a lowtemperature process, such as, the metal-induced crystallization. Furthermore, the floating gate a-Si:H TFT nonvolatile memories can then be constructed near the top layer of the interconnect structure at a temperature lower then the typical interconnect process temperature. Finally, a-Si:H based sensors can be added on top of the chip to detect changes of light, humidity, etc. Signals of environmental changes can be fed to the 3D circuit to adjust it functions, e.g., speed, memory, or energy consumption. The a-Si:H pin diode has been fabricated on top of an ASIC as the photo sensor.⁸⁸⁾ However, the split-gate a-Si:H TFT can also be used as a photo sensor, which does not require the low dopant efficiency pþ thin film deposition step^.75) In addition, special materials or structures of the a-Si:H TFT can be used to detect other environmental parameters, such as the pH value in a solution or the components in a gas stream. Since the source, drain, and gate electrodes of all these TFTs can be made of the same interconnect metal of the ULSIC, only a couple of extra masks are required to complete the TFT. In principle, this kind of conceptual chip can be constructed with the current process technology. However, for the actual operation, issues, such as process compatibility, reliability, and heat dissipation, need to be investigated in detail.

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