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Plasma etching in ULSIC is mainly used on low pressure CVD (LPCVD) or sputtered thin films with a preferred vertical profile. The most common etching damage is the charge neutralization caused breakdown of the thin gate dielectric. Plasma etching is also critical to the TFT array fabrication. Most of the etched thin films are deposited by PECVD, such as a-Si:H, SiNx, or nþ, or sputtering, such as refractory metals. The former has a high hydrogen content, which corresponding to a high etch rate but low etch selectivity between two films. The plasma chemistry and the ion bombardment energy are both important to the etch process.^33–35) Plasma etch induced damages in the a-Si:H TFT are mainly from the short wavelength light radiation, which can be repaired by a thermal annealing step.³⁶⁾ For the latter, when the gate line is etched, a sloped profile is necessary.^37,38) These problems are rarely discussed in ULSICs. However, low thermal budget processes, such as PECVD, are important to nano-size MOSFET fabrication. In another case, the high-k gate dielectric contains noncovalent bonds that are subject to plasma radiation damages. Therefore, the TFT plasma etching results are potentially important to the future generation ULSIC fabrication.

2.3 Simplified fabrication processes

The dramatic ramp up the large-area TFT array production throughput is greatly contributed by the aggressive reduction of the number of masks, e.g., from 7 – 8 masks in early 1990’s to 4 – 5 masks in recent years.³⁹⁾ For the TFT fabrication alone, the minimum number of required masks is 2.⁴⁰⁾ These low-mask count processes are accomplished due to the fully utilization of unique material, structure, and substrate properties as well as novel designs. In addition to lowering the cost, the product’s performance and reliability were not compromised. The same trend of reduction of number of masks in ULSIC fabrication has been explored. For example, methods, such as self-aligned ion implantation or silicide formation, have been used for many years. A fivemask CMOS process has also been reported.⁴¹⁾ Today, it still takes tens of masking steps to fabricate a complete chip. Therefore, the TFT’s experience in minimizing the number of masks may be useful to ULSICs.

2.4 Large-area laser processes

Laser crystallization is one of the most critical process steps in preparing high mobility, low threshold voltage, and low subthreshold slope poly-Si TFTs.⁴²⁾ Novel laser crystallization techniques, such as the metal-induced, lateral crystal growth, phase-modulated, or selective re-radiation method, have been used to prepare poly-Si thin films.^43–46) Laser processes have been used in producing poly-Si TFTs on large-area glass substrates. For advanced ULSIC fabrication, laser has been used in preparing submicron structures, such as filling the small vias with the deposited Al or Cu film, shallow junction doping, activation of implanted dopants, and formation of a thin gate oxide layer.^47–49) However, laser processing is rarely used in mass production of ULSICs probably due to the concern of large-area issues. Therefore, the TFT experience in laser processing may be a great help to the ULSIC production especially on large size wafers.

2.5 High-k gate dielectrics

Since the early development of the large-area a-Si:H TFT array fabrication, high-k dielectrics, such as SiNx, Ta₂O₅, HfO₂, or Al₂O₃, have been used as the gate dielectric material.^50–53) Due to its high k value, a physically relative thick film can be used to avoid the shortage between the top (source/drain) and bottom (gate) metals as well as to reduce the gate current leakage. However, in order to achieve the best device characteristics, such as high field effect mobility, low interface density of states, and the low threshold voltage, the high-k material is used as the bulk gate dielectric film with a separate SiNx interface layer in contact with a-Si:H.^54,55) The interface SiNx layer usually contains nonstoichiometric composition, smooth interface, low stress, low defect density, etc.^30,56,57) For sub 65 nm MOSFETs, a high-k material is required to replace the sub 1.2 nm thick thermal SiO2 gate dielectric to reduce the leakage current, to eliminate the diffusion of dopants to the channel region, and to improve device reliability.⁵⁸⁾ However, when the metal oxide high-k film is in direct contact with the silicon substrate, under a high temperature thermal annealing condition, it forms a defective SiOx or silicate interface layer that lowers the effective dielectric constant and generates a high interface state density.^59–62) This problem could be solved by inserting an artificial interface layer of SiO2 or SiON.^63,64) This result is consistent with that of TFT. Furthermore, for nano-size devices, the interface structure and properties are sensitive to the fabrication process condition. There is a general trend of preparing the ultrathin film under the non-equilibrium thermodynamic condition, such as the flash or pulsed thermal annealing, plasma exposures, or graded thin films. For example, our recent result showed that the sub 1 nm equivalent oxide thickness (EOT) high-k stack was achieved with a proper interface layer structure prepared under a tight annealing condition.⁶⁵⁾ Since most a-Si:H TFT processes are done at low temperatures and under thermodynamically non-equilibrium conditions, the experience would be useful for the nano-size device fabrication on large-size wafers.

2.6 Transistor structures

The structure of a transistor influences the device performance, product rel