可编程逻辑在数字信号处理系统中的应用
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER8B IS
PORT (CIN:IN STD_LOGIC;
A :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
OUT :OUT STD_LOGIC);
END ADDER8B;
ARCHIteCTURE struc OF ADDER8B IS
COMPONENT ADDER4B
PORT (CIN4: IN STD_LOGIC;
A4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4 : OUT ST_D_LOGIC_VECTOR(3 DOWN-TO 0);
COUT4 : OUT STD_LOGIC);
END COMPONENT;
SIGNAL CARRY_OUT : STD_LOGIC;
BEGIN
U1:ADDER4B
PORT MAP(CIN4=>CIN,A4=>A(3 DOWNTO 0),B4=>B(3 DOWNTO 0),S4=>S(3 DOWNTO 0),COUT4=>CARRY_OUT);
U2 :ADDER4B
PORT MAP(CIN4=>CARRY_OUT,A4=>A(7 DOWNTO 4),B4=>B(7 DOWNTO 4),S4=>S(7 DOWNTO 4),COUT4=>COUT);
END struc;
在上面的VHDL描述中,ADDER4B是一个4位二进制加法器,其VHDL描述是:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER4B IS
PORT (CIN4 :IN STD_LOGIC;
A4 :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT4:OUT STD_LOGIC;
EAND ADDER4B;
ARCHITEC_TURE behav OF ADDER4B IS
SIGNAL SINT :STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL AA,BB:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
AA=‘0’A4;
BB=‘0’B4;
SINT=AA+BB+CIN4;
S4=SINT(3 DOWNTO 0);
COUT4=SINT(4);
END behav;
4、结束语
本文采用基于EDA技术的自上而下的系统设计方法,其设计流程如图2所示。该乘法器的最大优点是节省芯片资源,其运算速度取决于输入的时钟频率。如若时钟频率为100MHz,则每个运算周期仅需80ns,因而具有一定的实用价值。
图2 VHDL设计流程
![](https://webstorage.eepw.com.cn/images/2014/m/wx.png)
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